Programme
Monday, 16th March |
|
| 09:00 |
Registration
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| ARC 2009 Venue: Tulla Hörsaal | |
| 10:00 |
European Projects Session
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| A series of presentations on EU-funded research projects: 10:00-10:40 Philippe Bonnot, MORPHEUS project 10:40-11:20 Gerard Smit (University of Twente), 4s project 11.20-12.00 Christian Gamrat, AETHER project Session Chair: Ralf König |
|
| 12:00 |
Lunch
|
| 13:15 |
ARC 2009 Workshop Opening Remarks
|
| 13:30 |
Keynote 1 :: Ian Phillips
Roger Woods
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| The Colour of Embedded Computation | |
| 14:15 |
Break
|
| 14:30 |
OS-1
Applications 1
Miguel Arias
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|
A HyperTransport 3 Physical Layer Interface for FPGAs
Parametric Design for Reconfigurable Software-Defined Radio
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|
| 15:20 |
Break
|
| 15:30 |
OS-2
Applications 2
Pedro Diniz
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Hardware/Software FPGA Architecture for Robotics Applications
Reconfigurable Operator Based Multimedia Embedded Processor
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|
| 16:20 |
Break
|
| 16:30 |
OS-3
FPGA Security and Bitstream analysis
Peter Athanas
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A Protocol for Secure Remote Updates of FPGA Configurations
FPGA Analysis Tool: High-level flows for low-level design analysis in reconfigurable computing
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|
| 19:00 |
Conference Dinner
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Gastdozentenhaus "Heinrich Hertz" |
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Tuesday, 17th March |
|
| 09:00 |
Keynote 2 :: Brent Nelson
Peter Athanas
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| Productivity Issues in FPGA Application Development | |
| 09:45 |
Break
|
| 10:00 |
OS-4
Fault Tolerant Systems
Jesús Barba
|
|
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications
Timing driven placement for fault tolerant circuits implemented on SRAM-based FPGAs
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|
| 10:50 |
PS-1
Poster Session 1
Fearghal Morgan
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| Refreshments | |
|
SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems
A Parallel Branching Program Machine for Emulation of Sequential Circuits
Memory Sharing Approach for TMR Softcore Processor
The need for Reconfigurable Routers in Networks-on-Chip
Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder
Tile-Based Fault-Tolerant Approach using Partial Reconfiguration
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|
| 11:45 |
OS-5
Architectures
João M. P. Cardoso
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A Novel Local Interconnect Architecture for Variable Grain Logic Cell
Dynamically Adapted Low Power ASIPs
Fast optical reconfigurations of a nine-context DORGA
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|
| 13:00 |
Lunch
|
| 14:00 |
OS-6
Place and Route Techniques
Hiroshi Kadota
|
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Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep
On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks
A New Datapath Merging Method for Reconfigurable System
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|
| 15:15 |
PS-2
Poster Session 2
Michael Huebner
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| Refreshments | |
|
Regular Expression Pattern Matching Supporting Constrained Repetitions
Accelerating calculations on the RASC platform. A case study of the exponential function
AES-Galois Counter Mode encryption/decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications
CCproc: A custom VLIW cryptography co-processor for symmetric-key ciphers
Object Tracking and Motion Capturing in Hardware-Accelerated Multi-Camera System
Implementation of the AES algorithm for a reconfigurable, bit serial, fully pipelined architecture
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
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|
| 16:15 |
OS-7
Cryptography
Tsutomu Sasao
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Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA based SoC Platform
Fully Pipelined Hardware Implementation of 128-bit SEED Block Cipher Algorithm
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs
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|
| 17:45 |
Visit to Center for Art and Media
|
| Visit to Center for Art and Media |
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Wednesday, 18th March |
|
| 09:00 |
Keynote 3 :: Chris Philips
Fearghal Morgan
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| Resiliency in Elemental Computing | |
| 09:45 |
Break
|
| 10:00 |
OS-8
Resource Allocation and Scheduling
Joonseok Park
|
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Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures
Online Task Scheduling for the FPGA-based partially reconfigurable systems
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|
| 10:50 |
PS-3
Poster Session 3
Fearghal Morgan
|
| Refreshments | |
|
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia
Real Time Simulation In Floating Point Precision Using FPGA Computing
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem
A Seamless Virtualization Approach for Transparent Dynamical Function Mapping targeting Heterogeneous and Reconfigurable Systems
Pilpeline Scheduling with Input Port Constraints for an FPGA-based Biochemical Simulator
ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach
A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms
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|
| 11:45 |
OS-9
Applications 3
Mladen Berekovic
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Word-length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator
FPGA-based Anomalous trajectory detection using SOFM
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|
| 12:35 |
Closing Remarks
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